1. Field of the Invention
This invention relates to the field of data processing systems. More particularly, this invention relates to the serialisation of status register access operations within a data processing system.
2. Description of the Prior Art
It is known to provide data processing systems with status registers storing various architectural and/or micro-architectural variables. An example of such registers include the current program status register (CPSR), coprocessor system configuration registers and the like used within the processors designed by ARM Limited of Cambridge, England. When it is desired to perform an access to such status registers (either a read access or a write access), then the programmer will assume that the effect of all instructions preceding the status register access instruction within the program order will have had their effect upon the status register being accessed such that the access will not produce an incorrect result, e.g. returning a read result which is not up-to-date or performing a write to the status register out of program order. These problems are compounded within processors which execute instructions in parallel and/or execute instructions out-of-order.
One known way of addressing the problem of serialisation of status register access operations is to identify such status register access instructions before they are dispatched (i.e. sent to an associated processing pipeline for further queuing and/or execution) and then halting dispatch of further instructions such that the processing pipelines will drain and all instructions preceding the status register access instruction within the program order will complete before the status register access instruction is released for execution. While this approach can ensure proper serialisation, it suffers from the disadvantage that halting dispatch while the processing pipelines drain adversely effects instruction processing throughput.